1. Field of the Invention
The present invention relates to a semiconductor memory, and more specifically to a semiconductor memory capable of ensuring data holding power supply voltage.
2. Description of the Priro Art
In semiconductor memories each including static memory cells with high resistance polycrystalline silicon load elements, a value of power supply voltage for data holding is ensured in order to hold memory information with the aid of a battery.
In case ensurance of minimum data holding power supply voltage of 2.0 V is desired, for example, its test is conducted by writing any information in a semiconducor memory at ordinary power supply voltage (e.g., 5.0 V), and thereafter switching the operation to a standby state and then holding the memory for a predetermined time at the power supply voltage lowered to 2.0 V, and reading out the information from the memory after the power supply voltage is returned to the initial one to bring the operation into an active state, for judgement of the quality of the ensurance of the power supply voltage.
Data holding time in the test of the data holding power supply voltage is calculated supposing the resistance of the high resistance load element and any leakage source of driver transistors of the memory cells.
FIGS. 1A and 1B illustrate a circuit diagram of a memory cell in a prior art semiconductor memory, and an equivalent circuit of the same, respectively.
The memory cell 1 of the semiconductor memory is comprised of driver N channel MOS transistors Q1, Q2 having their gate connected with counterpart drains and sources connected with a ground potential, high resistance load resistors R1, R2 each connected between the drains of the MOS transistors Q1, Q2 and a power supply terminal (power supply voltage Vcc), and N channel MOS transistors Q3, Q4 having their gates connected with a word line WL and being connected between the drains of the MOS transistors Q1, Q2 and first and second bit lines.
The drains of the transistors Q1, Q2 serve as storage nodes N1, N2 which nodes typically possess node capacitance Cn and leakage resistance Rn if existent. In the following, for values of the load resistors R1,R2, a leakage resistor Rn, and a node capacitor Cn, identical symbols to those ones shall be applied.
High level voltage Vh of each storage node (N1, N2) of the memory cell is herein expressed by: EQU Vh=Vcc.multidot.Rn/(Rn+R1) (1)
In order for each storage node to keep the high level, the following conditions must be satisfied: EQU Vh=Vcc.multidot.Rn/(Rn+R1)&gt;Vt (2)
Herein, Vt designates threshold voltage of the transistors Q1 and Q2.
From the above equations (1) and (2), there is derived the following relation EQU Rn&gt;1.5.times.10.sup.12 [.OMEGA.]
with the assumption of Vt to be 0.75 V and Vcc 2 V for example.
Estimation of the time t1 at which the high level storage node N1 becomes 0.75 V provides: EQU t1=[Cn.multidot.Rn.multidot.R1.multidot.ln(Vcc/Ve)]/(Rn+R1)=9.19.times.10.s up.-3 s (about 9.2 ms)
under the conditions of: EQU Cn=10.times.10.sup.-15, EQU Rn=1.5.times.10.sup.12, EQU R1=2.5.times.10.sup.12,
Vcc=2.0, and PA1 Vt=0.75
Once the high level storage node N1 becomes lower than the threshold voltage 0.75 V of the MOS transistor Q2, the MOS transistor Q2 is switched off while the low level storage node N2 is electrically charged through the load resistor R2 and hence initiates to increase its voltage. Once the storage node N2 reaches voltage exceeding the threshold voltage of 0.75 V of the MOS transistor Q1, the MOS transistor Q1 is switched on, and hence the levels of the storage nodes N1 and N2 are completely reversed to bring the memory cell into a failure one. Now, estimation of the time t2 at which the low level storage node becomes 0.75 V provides: EQU t2=R1.multidot.Cn.multidot.ln(Vcc/(Vcc-Vt))=11.75 msec.
The data holding time t until the memory cell information is reversed is thus provided by: EQU t=9.2+11.75=25.32(ms)
Namely, a time greater than about 25.3 ms is required. Further, in the data holding power supply voltage test, time period T during which the high level information written in the memory cell reaches 2 V is required. The time T is expressed by: EQU T=R1.multidot.Cn.multidot.ln(E/Vo) (3)
where E denotes the high level voltage of the memory cell when the high level information has been written in the memory cell, and Vo is herein 2 V.
The written voltage E is typically lower than the operating power supply voltage by the threshold voltage Vt of the MOS transistor.
Assuming that the power supply voltage is 4.5 V for example, E=3.75 V. It is understood from the equation (3) that T requires 15.7 ms or longer. Provided herein the power supply voltage is lowered to write information in the memory cell, it is possible to shorten the foregoing time T, but this is only for low voltage-operational semiconductor memories, and is severe even for semiconductor memories capable of ensurance of low voltage operation if they are to operate at 3.5 V or lower. Assuming that the power supply voltage is 3.5 V, E is 2.75 V and hence T requires 7.9 ms or longer. In actual tests, the time T ranges from several hundreds milli-seconds to several seconds or longerbecause it should be set to be longer by one through two digits usuallly in view of variations of fabrication of such semiconductor memories.
Further, in the use thereof at low temperature, the load resistances R1 and R2 are increased at the rate of square so that t as well as T are further increased. Provided the time T is insufficient to permit the storage node of the memory cell to satisfactorily lower to 2 V, the time t is further prolonged as a matter of course.
The prior art semiconductor memory suffers as described above from a difficulty that data is written therein at ordinary operating power supply voltage even upon the data writing in the data holding power supply voltage test so that enormous testing time is wastfully required to constitute a hindrance to production.